The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Sep. 22, 2022
Applicant:

Disco Corporation, Tokyo, JP;

Inventors:

Shunsuke Teranishi, Tokyo, JP;

Zhiwen Chen, Tokyo, JP;

Kyosuke Kobinata, Tokyo, JP;

Akihito Kawai, Tokyo, JP;

Assignee:

DISCO CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 24/94 (2013.01); H01L 24/96 (2013.01); H01L 2224/94 (2013.01); H01L 2224/96 (2013.01);
Abstract

A method of manufacturing a layered device chip assembly includes forming first grooves in a first wafer, fixing the first wafer to a support body, grinding the first wafer to expose the first grooves, forming a first resin layer in the first grooves, simultaneously polishing the first wafer and the first resin layer to expose the first resin layer, forming second grooves in the second wafer, the second grooves having a width on the face side larger than a width of the first grooves and a width at groove bottoms that is smaller than the width on the face side of the second wafer, affixing the second wafer to the first wafer, grinding the second wafer to expose the second grooves on the reverse side thereof, forming a second resin layer in the second grooves, and dividing the first wafer and the second wafer into a plurality of assemblies.


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