The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Jun. 07, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ming-Yuan Wu, Hsinchu, TW;

Ka-Hing Fung, Hsinchu County, TW;

Min Jiao, Hsinchu, TW;

Da-Wen Lin, Hsinchu, TW;

Wei-Yuan Jheng, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H01L 21/02532 (2013.01); H01L 21/0259 (2013.01); H01L 21/0262 (2013.01); H01L 21/26513 (2013.01); H01L 21/266 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0191 (2025.01); H10D 84/859 (2025.01);
Abstract

Semiconductor devices and methods are provided. In an embodiment, a method includes providing a workpiece including a first hard mask layer on a top surface of a substrate, performing an ion implantation process to form a doped region in the substrate, after the performing of the ion implantation process, annealing the workpiece at temperature T. The method also includes selectively removing the first hard mask layer, after the selectively removing of the first hard mask layer, performing a pre-bake process at temperature T, and, after the performing of the pre-bake process, epitaxially growing a vertical stack of alternating channel layers and sacrificial layers on the substrate, where the temperature Tis lower than the temperature T


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