The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Nov. 10, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Yong-Jie Wu, Hsinchu, TW;

Yen-Chung Ho, Hsinchu, TW;

Hui-Hsien Wei, Taoyuan, TW;

Chia-Jung Yu, Hsinchu, TW;

Pin-Cheng Hsu, Zhubei, TW;

Feng-Cheng Yang, Zhudong Township, TW;

Chung-Te Lin, Taiwan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10D 64/01 (2025.01); H10D 99/00 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76834 (2013.01); H01L 21/76802 (2013.01); H01L 21/76885 (2013.01); H01L 23/5283 (2013.01); H10D 64/01 (2025.01); H10D 99/00 (2025.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01);
Abstract

A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.


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