The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2025
Filed:
Jul. 20, 2021
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Mao-Lin Huang, Hsinchu, TW;
Lung-Kun Chu, Hsinchu, TW;
Chung-Wei Hsu, Hsinchu, TW;
Jia-Ni Yu, Hsinchu, TW;
Kuo-Cheng Chiang, Hsinchu, TW;
Kuan-Lun Cheng, Hsinchu, TW;
Chih-Hao Wang, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H01L 21/28247 (2013.01); H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/0167 (2025.01); H10D 84/0172 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract
A method for processing an integrated circuit includes forming N-type and P-type gate all around transistors and core gate all around transistors. The method deposits a first metal gate layer for the P-type transistors and a second metal gate layer for the N-type transistors. The method forms a passivation layer in-situ with the metal gate layer of the P-type transistors.