The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Jul. 03, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Meng-Sheng Chang, Chubei, TW;

Chia-En Huang, Xinfeng Township, TW;

Gu-Huan Li, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
G11C 13/0028 (2013.01); G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 2213/79 (2013.01); H10B 63/30 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02);
Abstract

A memory device includes a bit line (BL); a source line (SL); and a plurality of non-volatile memory cells operatively coupled between the BL and SL, respectively. Each of the plurality of non-volatile memory cells includes a resistor with a variable resistance, a first transistor, and a second transistor that are coupled to each other in series. In response to a first one of the non-volatile memory cell not being read and a second one of the non-volatile memory cell being read, a voltage level at a first node connected between the first and second transistors of the first non-volatile memory cell is greater than zero.


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