The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Nov. 30, 2023
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Tsmc Nanjing Company, Limited, Nanjing, CN;

Inventors:

Hidehiro Fujiwara, Hsinchu, TW;

Tze-Chiang Huang, Hsinchu, TW;

Hong-Chen Cheng, Hsinchu, TW;

Yen-Huei Chen, Hsinchu, TW;

Hung-Jen Liao, Hsinchu, TW;

Jonathan Tsung-Yung Chang, Hsinchu, TW;

Yun-Han Lee, Hsinchu, TW;

Lee-Chung Lu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 11/418 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); G11C 11/418 (2013.01); H01L 21/76898 (2013.01); H10B 10/18 (2023.02);
Abstract

An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.


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