The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Jun. 13, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Cheng-Chin Lee, Taipei, TW;

Shao-Kuan Lee, Kaohsiung, TW;

Hsin-Yen Huang, New Taipei, TW;

Hai-Ching Chen, Hsinchu, TW;

Shau-Lin Shue, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 21/0228 (2013.01); H01L 21/02304 (2013.01); H01L 21/76837 (2013.01); H01L 21/76885 (2013.01); H01L 23/5222 (2013.01); H01L 23/5283 (2013.01);
Abstract

A method and structure for forming a barrier-free interconnect layer includes patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches. In some embodiments, the method further includes selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches. In some examples, and after selectively depositing the barrier layer, a dielectric layer is deposited within the one or more trenches. Thereafter, the selectively deposited barrier layer may be removed to form air gaps between the patterned metal layer and the dielectric layer.


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