The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2025

Filed:

Dec. 26, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Adel Elsherbini, Tempe, AZ (US);

Mauro Kobrinsky, Portland, OR (US);

Shawna Liff, Scottsdale, AZ (US);

Johanna Swan, Scottsdale, AZ (US);

Gerald Pasdast, San Jose, CA (US);

Sathya Narasimman Tiagaraj, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2005.12); H01L 21/768 (2005.12); H01L 23/522 (2005.12); H01L 23/528 (2005.12);
U.S. Cl.
CPC ...
H01L 23/5226 (2012.12); H01L 21/76816 (2012.12); H01L 21/76877 (2012.12); H01L 23/5283 (2012.12); H01L 23/5286 (2012.12);
Abstract

An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.


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