The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Jan. 03, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Perng-Fei Yuh, Walnut Creek, CA (US);

Yih Wang, Hsinchu, TW;

Meng-Sheng Chang, Hsinchu, TW;

Jui-Che Tsai, Tainan, TW;

Ku-Feng Lin, New Taipei, TW;

Yu-Wei Lin, Taichung, TW;

Keh-Jeng Chang, Hsinchu, TW;

Chansyun David Yang, Hsinchu, TW;

Shao-Ting Wu, Hsinchu, TW;

Shao-Yu Chou, Hsinchu County, TW;

Philex Ming-Yan Fan, Tainan, TW;

Yoshitaka Yamauchi, Hsinchu, TW;

Tzu-Hsien Yang, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/16 (2005.12); G11C 17/18 (2005.12); H10B 20/25 (2022.12);
U.S. Cl.
CPC ...
H10B 20/25 (2023.01); G11C 17/16 (2012.12); G11C 17/18 (2012.12);
Abstract

The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.


Find Patent Forward Citations

Loading…