The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Jul. 13, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Min-Feng Kao, Chiayi, TW;

Dun-Nian Yaung, Taipei, TW;

Jen-Cheng Liu, Hsin-Chu, TW;

Hsing-Chih Lin, Tainan, TW;

Zheng-Xun Li, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2005.12); H01L 21/768 (2005.12); H01L 23/48 (2005.12); H01L 23/522 (2005.12); H01L 23/528 (2005.12); H01L 25/00 (2005.12); H01L 25/065 (2022.12);
U.S. Cl.
CPC ...
H01L 24/80 (2012.12); H01L 21/76898 (2012.12); H01L 23/481 (2012.12); H01L 23/5226 (2012.12); H01L 23/5283 (2012.12); H01L 24/08 (2012.12); H01L 24/32 (2012.12); H01L 25/0657 (2012.12); H01L 25/50 (2012.12); H01L 2224/08146 (2012.12); H01L 2224/32146 (2012.12); H01L 2224/8038 (2012.12); H01L 2224/80894 (2012.12); H01L 2225/06544 (2012.12);
Abstract

A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure. A bonding feature of the second front-side bonding structure includes a first bonding via in contact with the second interconnect structure, a first bonding contact overlying the first bonding via, and a barrier layer interface between a bottom of the first bonding contact and a top of the first bonding via.


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