The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Oct. 25, 2021
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Yanwei Shi, Wuhan, CN;

Yanhong Wang, Wuhan, CN;

Cheng Gan, Wuhan, CN;

Liang Chen, Wuhan, CN;

Wei Liu, Wuhan, CN;

Zhiliang Xia, Wuhan, CN;

Wenxi Zhou, Wuhan, CN;

Kun Zhang, Wuhan, CN;

Yuancheng Yang, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2022.12); G11C 16/04 (2005.12); G11C 16/24 (2005.12); H01L 23/00 (2005.12); H01L 25/00 (2005.12); H01L 25/18 (2022.12); H10B 41/41 (2022.12); H10B 43/40 (2022.12);
U.S. Cl.
CPC ...
H01L 24/80 (2012.12); G11C 16/0483 (2012.12); G11C 16/24 (2012.12); H01L 24/08 (2012.12); H01L 25/0657 (2012.12); H01L 25/18 (2012.12); H01L 25/50 (2012.12); H10B 41/41 (2023.01); H10B 43/40 (2023.01); H01L 2224/08145 (2012.12); H01L 2224/80895 (2012.12); H01L 2224/80896 (2012.12); H01L 2924/1431 (2012.12); H01L 2924/14511 (2012.12);
Abstract

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recess gate transistor is formed on a second substrate. The recess gate transistor includes a recess gate structure protruding into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.


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