The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Oct. 04, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kenneth Chun Kuen Cheng, Shatin, HK;

Koichi Motoyama, Clifton Park, NY (US);

Kisik Choi, Watervliet, NY (US);

Cornelius Brown Peethala, Slingerlands, NY (US);

Hosadurga Shobha, Niskayuna, NY (US);

Joe Lee, Albany, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53266 (2013.01); H01L 21/02183 (2013.01); H01L 21/0228 (2013.01); H01L 21/76807 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 21/76849 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01);
Abstract

Bottom barrier free interconnects are provided. In one aspect, an interconnect structure includes: metal lines embedded in a dielectric; an interlayer dielectric (ILD) disposed over the metal lines; interconnects formed in the ILD on top of the metal lines; a barrier layer separating the interconnects from the ILD, wherein the barrier layer is absent in between the interconnects and the metal lines; and a selective capping layer disposed on the interconnects.


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