The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Jul. 07, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Huang-Jen Hsu, Hsinchu, TW;

Jheng-Si Su, Hsinchu, TW;

Kung-Ming Liu, Hsinchu, TW;

Tzuyi Hsieh, Hsinchu, TW;

Feng-Inn Wu, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 21/02118 (2013.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/31053 (2013.01); H01L 29/0649 (2013.01); H01L 2223/54426 (2013.01);
Abstract

The current disclosure describes techniques for making an alignment mark on a wafer. A recess is etched in a first surface region of a wafer. A device structure is formed in a second surface region of the wafer. A dielectric layer is deposited on the first surface of the wafer and filling the recess. A first planarization procedure is conducted to planarize the dielectric layer. After the first planarization procedure, a second planarization procedure is conducted to device structures on the second surface region of the wafer.


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