The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2025
Filed:
Dec. 13, 2019
Intel Corporation, Santa Clara, CA (US);
Tanuj Trivedi, Hillsboro, OR (US);
Rahul Ramaswamy, Portland, OR (US);
Jeong Dong Kim, Scappoose, OR (US);
Ting Chang, Portland, OR (US);
Walid M. Hafez, Portland, OR (US);
Babak Fallahazad, Portland, OR (US);
Hsu-Yu Chang, Hillsboro, OR (US);
Nidhi Nidhi, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments disclosed herein include nanowire and nanoribbon devices with non-uniform dielectric thicknesses. In an embodiment, the semiconductor device comprises a substrate and a plurality of first semiconductor layers in a vertical stack over the substrate. The first semiconductor layers may have a first spacing. In an embodiment, a first dielectric surrounds each of the first semiconductor layers, and the first dielectric has a first thickness. The semiconductor device may further comprise a plurality of second semiconductor layers in a vertical stack over the substrate, where the second semiconductor layers have a second spacing that is greater than the first spacing. In an embodiment a second dielectric surrounds each of the second semiconductor layers, and the second dielectric has a second thickness that is greater than the first thickness.