The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2025
Filed:
Sep. 13, 2021
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Ching-Wei Tsai, Hsinchu, TW;
Yu-Xuan Huang, Hsinchu, TW;
Kuan-Lun Cheng, Hsin-chu, TW;
Chih-Hao Wang, Baoshan Township Hsinchu County, TW;
Min Cao, Hsinchu, TW;
Jung-Hung Chang, Changhua County, TW;
Lo-Heng Chang, Hsinchu, TW;
Pei-Hsun Wang, Kaohsiung, TW;
Kuo-Cheng Chiang, Zhubei, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.