The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

Jul. 26, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Jia-Ni Yu, New Taipei, TW;

Kuo-Cheng Chiang, Hsinchu, TW;

Lung-Kun Chu, New Taipei, TW;

Chung-Wei Hsu, Hsinchu, TW;

Chih-Hao Wang, Hsinchu, TW;

Mao-Lin Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 29/7855 (2013.01);
Abstract

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.


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