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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12232320 B1

PDFFull Text
Date of Patent:
Feb. 18, 2025

Filed:

Aug. 22, 2023

Word line structure of three-dimensional memory device

Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Qiang Xu, Wuhan, CN;

Fandong Liu, Wuhan, CN;

Zongliang Huo, Wuhan, CN;

Zhiliang Xia, Wuhan, CN;

Yaohua Yang, Wuhan, CN;

Peizhen Hong, Wuhan, CN;

Wenyu Hua, Wuhan, CN;

Jia He, Wuhan, CN;

Assignee:

YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan, CN;

Attorney:

BAYES PLLC

Primary Examiner:

Julia Slutsker

Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H10B 43/10 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 21/02164 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H10B 43/10 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02); H01L 21/02271 (2013.01); H01L 21/0262 (2013.01); H01L 21/28568 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01);
Abstract

A memory device includes a substrate, a stack over the substrate, and a gate line slit extending along a first direction and dividing the stack into two portions. The stack includes a connection portion that connects the two portions of the stack. The connection portion includes at least two sub-connection portions along a second direction perpendicular to the first direction. The gate line slit includes at least two portions along the first direction. Each sub-connection portion is between adjacent two portions of the gate line slit.

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