The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2025

Filed:

Apr. 14, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Yong-Jie Wu, Hsinchu, TW;

Yen-Chung Ho, Hsinchu, TW;

Hui-Hsien Wei, Taoyuan, TW;

Chia-Jung Yu, Hsinchu, TW;

Pin-Cheng Hsu, Zhubei, TW;

Mauricio Manfrini, Zhubei, TW;

Chung-Te Lin, Taiwan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 61/00 (2023.01); H01L 21/02 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 53/30 (2023.01); H10B 63/00 (2023.01); H10N 50/01 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H10B 61/22 (2023.02); H01L 21/02565 (2013.01); H01L 29/24 (2013.01); H01L 29/66969 (2013.01); H01L 29/78645 (2013.01); H01L 29/7869 (2013.01); H10B 53/30 (2023.02); H10B 63/30 (2023.02); H10N 50/01 (2023.02); H10N 70/063 (2023.02);
Abstract

A memory structure includes: first and second word lines; a high-k dielectric layer disposed on the first and second word lines; a channel layer disposed on the high-k dielectric layer and comprising a semiconductor material; first and second source electrodes electrically contacting the channel layer; a first drain electrode disposed on the channel layer between the first and second source electrodes; a memory cell electrically connected to the first drain electrode; and a bit line electrically connected to the memory cell.


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