The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2025
Filed:
Aug. 10, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Fong-Yuan Chang, Hsinchu, TW;
Chin-Chou Liu, Hsinchu, TW;
Hui-Zhong Zhuang, Hsinchu, TW;
Meng-Kai Hsu, Hsinchu, TW;
Pin-Dai Sue, Hsinchu, TW;
Po-Hsiang Huang, Hsinchu, TW;
Yi-Kan Cheng, Hsinchu, TW;
Chi-Yu Lu, Hsinchu, TW;
Jung-Chou Tsai, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.