The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2025
Filed:
Aug. 17, 2023
Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US);
Guilian Gao, San Jose, CA (US);
Bongsub Lee, Santa Clara, CA (US);
Gaius Gillman Fountain, Jr., Youngsville, NC (US);
Cyprian Emeka Uzoh, San Jose, CA (US);
Belgacem Haba, Saratoga, CA (US);
Laura Wills Mirkarimi, Sunol, CA (US);
Rajesh Katkar, Milpitas, CA (US);
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US);
Abstract
Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a through-silicon via (TSV) may be disposed through at least one of the microelectronic substrates. The TSV is exposed at the bonding interface of the substrate and functions as a contact surface for direct bonding.