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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12199190 B1

PDFFull Text
Date of Patent:
Jan. 14, 2025

Filed:

Jun. 05, 2023

Silicon channel tempering

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Mao-Lin Huang, Hsinchu, TW;

Jia-Ni Yu, New Taipei, TW;

Lung-Kun Chu, New Taipei, TW;

Chung-Wei Hsu, Hsinchu, TW;

Chih-Hao Wang, Hsinchu, TW;

Kuo-Cheng Chiang, Hsinchu County, TW;

Kuan-Lun Cheng, Hsin-Chu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

HAYNES AND BOONE, LLP

Primary Examiner:

Brian Turner

Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); H01L 21/02236 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/0262 (2013.01); H01L 21/28185 (2013.01); H01L 21/823807 (2013.01); H01L 27/092 (2013.01); H01L 29/0653 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78684 (2013.01);
Abstract

A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.

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