The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Mar. 26, 2021
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Bin Yuan, Wuhan, CN;

Zhu Yang, Wuhan, CN;

Xiangning Wang, Wuhan, CN;

Chen Zuo, Wuhan, CN;

Jingjing Geng, Wuhan, CN;

Zhen Guo, Wuhan, CN;

Zongke Xu, Wuhan, CN;

Qiangwei Zhang, Wuhan, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 41/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 41/27 (2023.02);
Abstract

Aspects of the disclosure provide methods for fabricating semiconductor devices. In some examples, a method for fabricating a semiconductor device includes forming a stack of layers having a first region and a second region. The stack of layers includes at least a first layer. The method then forms a hard mask layer on the stack of layers in the first region. Then, the method includes patterning the stack of layers in the second region of the semiconductor device. The patterning of the stack of layers in the second region removes a portion of the stack of layers in the second region, and exposes a side of the stack of layers. The method further includes covering at least the side of the stack of layers with a second layer that has a lower remove rate than the first layer, and then the method includes removing the hard mask layer.


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