The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Dec. 22, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sudipto Naskar, Portland, OR (US);

Willy Rachmady, Beaverton, OR (US);

Hsin-Fen Li, Hillsboro, OR (US);

Christopher Parker, Portland, OR (US);

Prashant Wadhwa, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Mohammad Hasan, Aloha, OR (US);

Jianqiang Lin, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); B82Y 10/00 (2011.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H01L 29/42392 (2013.01); H01L 27/088 (2013.01); H01L 29/41733 (2013.01); H01L 29/78696 (2013.01);
Abstract

A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer.


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