The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2024

Filed:

Jul. 26, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chung-Wei Hsu, Hsinchu, TW;

Kuo-Cheng Chiang, Hsinchu County, TW;

Kuan-Lun Cheng, Hsin-Chu, TW;

Hou-Yu Chen, Hsinchu County, TW;

Ching-Wei Tsai, Hsinchu, TW;

Chih-Hao Wang, Hsinchu County, TW;

Lung-Kun Chu, New Taipei, TW;

Mao-Lin Huang, Hsinchu, TW;

Jia-Ni Yu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823857 (2013.01); H01L 21/02236 (2013.01); H01L 21/02603 (2013.01); H01L 21/28185 (2013.01); H01L 21/31111 (2013.01); H01L 21/823807 (2013.01); H01L 27/092 (2013.01); H01L 29/0673 (2013.01); H01L 29/42364 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/516 (2013.01); H01L 29/66742 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H01L 29/78696 (2013.01); H01L 2029/42388 (2013.01);
Abstract

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.


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