The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Jan. 31, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Min-Kun Dai, Hsinchu, TW;

Yen-Chieh Huang, Changhua County, TW;

Kuo-Chang Chiang, Hsinchu, TW;

Han-Ting Tsai, Kaoshiung, TW;

Tsann Lin, Hsinchu, TW;

Chung-Te Lin, Tainan, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/30 (2023.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H10B 51/30 (2023.02); H01L 29/40111 (2019.08); H01L 29/66969 (2013.01); H01L 29/78391 (2014.09); H01L 29/7869 (2013.01);
Abstract

A method of forming a semiconductor structure includes following operations. A memory layer is formed over the first gate electrode. A channel layer is formed over the memory layer. A first SUT treatment is performed. A second dielectric layer is formed over the memory layer and the channel layer. A source electrode and a drain electrode are formed in the second dielectric layer. A temperature of the first SUT treatment is less than approximately 400° C.


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