The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Aug. 03, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Han-Tang Hung, ShinChu, TW;

Shin-Yi Yang, New Taipei, TW;

Ming-Han Lee, Taipei, TW;

Shau-Lin Shue, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 21/78 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 24/73 (2013.01); H01L 24/94 (2013.01); H01L 25/50 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/73204 (2013.01);
Abstract

Embodiments of the present disclosure provide a semiconductor package. In one embodiment, the semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die comprises a first device layer and a first interconnect structure. The semiconductor package also includes a second integrated circuit die having a second circuit design different than the first circuit design, and the second integrated circuit die comprises a second device layer and a second interconnect structure having a first side in contact with the first device layer and a second side in direct contact with the first interconnect structure of the first integrated circuit die. The semiconductor package further includes a substrate having a first side bonded to the first interconnect structure, wherein the second integrated circuit die is surrounded by at least a portion of the substrate.


Find Patent Forward Citations

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Hung, Han-Tang. (2024). Semiconductor packages and methods for forming the same (U.S. Patent No. 12166026). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12166026

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