The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Apr. 29, 2021
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Xinru Zeng, Hubei, CN;

Peng Chen, Hubei, CN;

Meng Wang, Hubei, CN;

Baohua Zhang, Hubei, CN;

Houde Zhou, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 41/27 (2013.01); H01L 21/48 (2006.01); H01L 21/50 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); H01L 21/60 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/4853 (2013.01); H01L 21/50 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/14 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H01L 2021/60022 (2013.01); H01L 2224/02321 (2013.01);
Abstract

The present disclosure includes a semiconductor package including a redistribution layer (RDL) having a first surface in contact with input/output (I/O) contacts and a second surface opposite to the first surface. The semiconductor package also includes a staircase interconnect structure formed on the second surface of the RDL and electrically connected with the RDL. The staircase interconnect structure includes staircase layers including a first staircase layer and a second staircase layer stacked on a top surface of the first staircase layer. The second staircase layer covers a portion of the top surface of the first staircase layer such that a remaining portion of the top surface of the first staircase layer is exposed. Integrated circuit (IC) chips are electrically connected to the RDL via the staircase interconnect structure. A first IC chip of the IC chips is electrically connected to the RDL through the remaining portion of the top surface of the first staircase layer.


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