The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Mar. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wen-Sheh Huang, Hsinchu, TW;

Yung-Shih Cheng, Hsinchu, TW;

Jiing-Feng Yang, Hsinchu County, TW;

Yu-Hsiang Chen, Hsinchu, TW;

Chii-Ping Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 21/02 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/535 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3731 (2013.01); H01L 21/02603 (2013.01); H01L 21/4807 (2013.01); H01L 21/76895 (2013.01); H01L 23/5228 (2013.01); H01L 23/535 (2013.01); H01L 29/0673 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.


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