The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2024

Filed:

Oct. 31, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Woochan Kim, Sunnyvale, CA (US);

Masamitsu Matasuura, Beppu, JP;

Mutsumi Masumoto, Beppu, JP;

Kengo Aoya, Beppu, JP;

Hau Thanh Nguyen, San Jose, CA (US);

Vivek Kishorechand Arora, San Jose, CA (US);

Anindya Poddar, Sunnyvale, CA (US);

Hideaki Matsunaga, Beppu, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/4853 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3107 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2224/214 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/1033 (2013.01);
Abstract

In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.


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