The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Dec. 07, 2021
Applicant:

Panjit International Inc., Kaohsiung, TW;

Inventors:

Chung-Hsiung Ho, Kaohsiung, TW;

Wei-Ming Hung, Kaohsiung, TW;

Wen-Liang Huang, Kaohsiung, TW;

Shun-Chi Shen, Kaohsiung, TW;

Chien-Chun Wang, Tainan, TW;

Chi-Hsueh Li, Tainan, TW;

Assignee:

Panjit International Inc., Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3107 (2013.01); H01L 21/4814 (2013.01); H01L 21/568 (2013.01); H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 24/29 (2013.01); H01L 2224/08235 (2013.01); H01L 2224/29147 (2013.01);
Abstract

The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.


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