The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2024

Filed:

Aug. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wei-Han Fan, Hsinchu, TW;

Wei-Yang Lee, Taipei, TW;

Tzu-Hua Chiu, Hsinchu, TW;

Chia-Pin Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/768 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/401 (2013.01); H01L 21/76897 (2013.01); H01L 29/41733 (2013.01); H01L 29/41791 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method of forming a semiconductor including forming a source/drain feature adjacent to a semiconductor layer stack disposed over a substrate. The method further includes forming a dummy fin adjacent to the source/drain feature and adjacent to the semiconductor layer stack. The method further includes performing an etching process from a backside of the substrate to remove a first portion of the dummy fin adjacent to the source/drain feature, thereby forming a first trench in the dummy fin, where the first trench extends from the dummy fin to the source/drain feature. The method further includes forming a first dielectric layer in the first trench and replacing a second portion of the dummy fin with a source/drain contact.


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