The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 29, 2024
Filed:
Jun. 01, 2022
Intel Ndtm Us Llc, Santa Clara, CA (US);
Chao Zhang, Milpitas, CA (US);
Krishna Parat, Palo Alto, CA (US);
Richard Fastow, Cupertino, CA (US);
Ricardo Basco, Santa Clara, CA (US);
Xin Sun, Fremont, CA (US);
Heonwook Kim, Santa Clara, CA (US);
Zhan Liu, Santa Clara, CA (US);
Intel NDTM US LLC, Santa Clara, CA (US);
Abstract
Systems, apparatuses and methods may provide for technology that biases a word line of a block in NAND memory to a first voltage level, biases a source-side select gate and a drain-side select gate of the block to a second voltage level, and issues a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse. In one example, the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block.