The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2024
Filed:
Jul. 06, 2021
Intel Corporation, Santa Clara, CA (US);
Wilfred Gomes, Portland, OR (US);
Mauro J. Kobrinsky, Portland, OR (US);
Abhishek A. Sharma, Hillsboro, OR (US);
Rajesh Kumar, Portland, OR (US);
Kinyip Phoa, Beaverton, OR (US);
Elliot Tan, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Swaminathan Sivakumar, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.