The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2024
Filed:
Dec. 18, 2020
Intel Corporation, Santa Clara, CA (US);
Michael Makowski, Beaverton, OR (US);
Sudipto Naskar, Portland, OR (US);
Ryan Pearce, Beaverton, OR (US);
Nita Chandrasekhar, Portland, OR (US);
Minyoung Lee, Vancouver, WA (US);
Christopher Parker, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Transistors structures comprising a semiconductor features and dielectric material comprising silicon and oxygen in gaps or spaces between the features. The dielectric material may fill the gaps from bottom-up with an atomic layer deposition (ALD) process that includes a silicon deposition phase, and an oxidation phase augmented by N:NHplasma activated nitrogen species. Being plasma activated, the nitrogen species have short mean free paths, and therefore preferentially passivate surfaces with low aspect ratios. This aspect-ratio dependent passivation may increase an energy barrier to surface reactions with a silicon precursor, resulting in a concomitant differential in deposition rate. With N:NHplasma passivation, deposited dielectric material may have a nitrogen concentration that varies by at least order of magnitude as a function of the aspect ratio of the filled gaps.