The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2024
Filed:
Jul. 31, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Chia-Hao Pao, Hsinchu, TW;
Chih-Chuan Yang, Tainan, TW;
Shih-Hao Lin, Hsinchu, TW;
Kian-Long Lim, Hsinchu, TW;
Chih-Wei Lee, Hsinchu, TW;
Chien-Yuan Chen, Hsinchu, TW;
Jo-Chun Hung, Hsinchu, TW;
Yung-Hsiang Chan, Hsinchu, TW;
Yu-Kuan Lin, Hsinchu, TW;
Lien-Jung Hung, Taipei, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.