The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Apr. 19, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yu-Sheng Wang, Tainan, TW;

Chi-Cheng Hung, Tainan, TW;

Chen-Yuan Kao, Zhudong Township, TW;

Yi-Wei Chiu, Kaohsiung, TW;

Liang-Yueh Ou Yang, New Taipei, TW;

Yueh-Ching Pai, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/288 (2006.01); H01L 23/485 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76895 (2013.01); H01L 21/2885 (2013.01); H01L 21/76829 (2013.01); H01L 21/76831 (2013.01); H01L 21/7684 (2013.01); H01L 21/76849 (2013.01); H01L 21/76874 (2013.01); H01L 21/76877 (2013.01); H01L 21/76879 (2013.01); H01L 21/76883 (2013.01); H01L 29/41775 (2013.01); H01L 29/66477 (2013.01); H01L 29/665 (2013.01); H01L 29/66553 (2013.01); H01L 29/78 (2013.01); H01L 29/7833 (2013.01); H01L 21/28518 (2013.01); H01L 21/76843 (2013.01); H01L 21/76855 (2013.01); H01L 21/76873 (2013.01); H01L 23/485 (2013.01);
Abstract

A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.


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