The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Jun. 25, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Nicole Thomas, Portland, OR (US);

Michael K. Harper, Hillsboro, OR (US);

Leonard P. Guler, Hillsboro, OR (US);

Marko Radosavljevic, Portland, OR (US);

Thoe Michaelos, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42392 (2013.01); H01L 21/0228 (2013.01); H01L 21/76897 (2013.01); H01L 21/823412 (2013.01); H01L 29/0669 (2013.01);
Abstract

Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.


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