The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Nov. 23, 2022
Applicant:

Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US);

Inventors:

Cyprian Emeka Uzoh, San Jose, CA (US);

Jeremy Alfred Theil, Mountain View, CA (US);

Liang Wang, Newark, CA (US);

Rajesh Katkar, Milpitas, CA (US);

Guilian Gao, San Jose, CA (US);

Laura Wills Mirkarimi, Sunol, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/26 (2013.01); H01L 24/03 (2013.01); H01L 24/09 (2013.01); H01L 24/27 (2013.01); H01L 24/30 (2013.01); H01L 24/83 (2013.01); H01L 2224/08257 (2013.01); H01L 2924/01025 (2013.01); H01L 2924/01027 (2013.01); H01L 2924/01028 (2013.01);
Abstract

Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.


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