The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2024

Filed:

Feb. 22, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jianfeng Hu, Shanghai, CN;

Zhicheng Ding, Shanghai, CN;

Yong She, Shanghai, CN;

Zhijun Xu, Shanghai, CN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/83 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 2224/26152 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32237 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73263 (2013.01); H01L 2924/35121 (2013.01);
Abstract

Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a plurality of cavities, and a plurality of adhesives in the cavities of the package substrate. The semiconductor package also includes a plurality of stacked dies over the adhesives and the package substrate, where the stacked dies are coupled to the adhesives with spacers. The spacers may be positioned below outer edges of the stacked dies. The adhesives may include a plurality of films. The semiconductor package may further include a plurality of interconnects coupled to the stacked dies and package substrate, a plurality of electrical components on the package substrate, a mold layer over the stacked dies, interconnects, spacers, adhesives, and electrical components, and a plurality of adhesive layers coupled to the plurality of stacked dies, where one of the adhesive layers couples the stacked dies to the spacers.


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