The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2024
Filed:
Jul. 31, 2019
Applicant:
Lam Research Corporation, Fremont, CA (US);
Inventors:
Xiaolan Ba, San Jose, CA (US);
Ruopeng Deng, San Jose, CA (US);
Juwen Gao, San Jose, CA (US);
Sanjay Gopinath, Fremont, CA (US);
Lawrence Schloss, Palo Alto, CA (US);
Assignee:
Lam Research Corporation, Fremont, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/285 (2006.01); C23C 10/04 (2006.01); C23C 16/04 (2006.01); C23C 16/14 (2006.01); C23C 16/455 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H01L 21/28568 (2013.01); C23C 16/045 (2013.01); C23C 16/14 (2013.01); C23C 16/45527 (2013.01); C23C 16/45544 (2013.01); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/53209 (2013.01); H01L 23/53242 (2013.01); H01L 23/53257 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02);
Abstract
Described herein are methods and apparatuses for filling semiconductor substrate structures with conductive material. The methods involve depositing multi-layer bulk metal films in structures with one or more deposition conditions changed when transitioning from layer-to-layer. The methods result in high fill quality, high throughput, low precursor consumption, and low roughness. Multi-station chambers to perform the methods are also provided.