The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2024

Filed:

Aug. 16, 2022
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Daniel J. Fulford, Ballston Lake, NY (US);

Anthony R. Schepis, Averill Park, NY (US);

Mark I. Gardner, Cedar Creek, TX (US);

Anton J. Devilliers, Clifton Park, NY (US);

H. Jim Fulford, Marianna, FL (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/20 (2006.01); G03F 7/00 (2006.01);
U.S. Cl.
CPC ...
G03F 7/70633 (2013.01); G03F 7/70625 (2013.01);
Abstract

Aspects of the present disclosure provide a method for improving overlay alignment of patterning by correcting wafer shape. For example, the method can include receiving a wafer having a working surface with at least partially-fabricated semiconductor devices, and a backside surface opposite to the working surface. The method can also include forming a first stressor film on the backside surface. The first stressor film can modify overlay alignment of the working surface in a first direction across the working surface of the wafer. The method can also include forming one or more first semiconductor structures on the working surface of the wafer. The first semiconductor structures are aligned in the first direction.


Find Patent Forward Citations

Loading…