The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 2024
Filed:
Feb. 14, 2023
Intel Corporation, Santa Clara, CA (US);
Travis W. Lajoie, Forest Grove, OR (US);
Abhishek A. Sharma, Hillsboro, OR (US);
Van H. Le, Portland, OR (US);
Chieh-Jen Ku, Hillsboro, OR (US);
Pei-Hua Wang, Beaverton, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Bernhard Sell, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Gregory George, Beaverton, OR (US);
Akash Garg, Portland, OR (US);
Julie Rollins, Forest Grove, OR (US);
Allen B. Gardiner, Portland, OR (US);
Shem Ogadhoh, Beaverton, OR (US);
Juan G. Alzate Vinasco, Tigard, OR (US);
Umut Arslan, Portland, OR (US);
Fatih Hamzaoglu, Portland, OR (US);
Nikhil Mehta, Portland, OR (US);
Yu-Wen Huang, Beaverton, OR (US);
Shu Zhou, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.