The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Sep. 25, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Dheeraj Subbareddy, Portland, OR (US);

Ankireddy Nalamalpu, Portland, OR (US);

Anshuman Thakur, Beaverton, OR (US);

Md Altaf Hossain, Portland, OR (US);

Mahesh Kumashikar, Bangalore, IN;

Kemal Aygün, Tempe, AZ (US);

Casey Thielen, Chandler, AZ (US);

Daniel Klowden, Portland, OR (US);

Sandeep B. Sane, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 30/30 (2020.01); G06F 30/347 (2020.01);
U.S. Cl.
CPC ...
G06F 13/4221 (2013.01); G06F 13/4282 (2013.01); G06F 30/30 (2020.01); G06F 30/347 (2020.01); G06F 2213/0026 (2013.01);
Abstract

Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.


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