The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Dec. 13, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chung-Wei Hsu, Hsinchu County, TW;

Chih-Hao Wang, Hsinchu County, TW;

Huan-Chieh Su, Changhua County, TW;

Wei-Hao Wu, Hsinchu, TW;

Zhi-Chang Lin, Hsinchu County, TW;

Jia-Ni Yu, New Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/28088 (2013.01); H01L 21/28114 (2013.01); H01L 21/76832 (2013.01); H01L 29/42376 (2013.01); H01L 29/4966 (2013.01); H01L 29/51 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01);
Abstract

Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.


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