The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Dec. 23, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Hsu-Yu Chang, Hillsboro, OR (US);

Neville L. Dias, Hillsboro, OR (US);

Walid M. Hafez, Portland, OR (US);

Chia-Hong Jan, Portland, OR (US);

Roman W. Olac-Vaw, Hillsboro, OR (US);

Chen-Guan Lee, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1054 (2013.01); H01L 21/26506 (2013.01); H01L 21/26586 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66659 (2013.01); H01L 29/7848 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01);
Abstract

Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.


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