The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Jun. 30, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Anindya Poddar, Sunnyvale, CA (US);

Ashok Surendra Prabhu, San Jose, CA (US);

Hau Nguyen, San Jose, CA (US);

Kurt Edward Sincerbox, San Jose, CA (US);

Makoto Shibuya, Tokyo, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 24/94 (2013.01); H01L 21/4825 (2013.01); H01L 21/4839 (2013.01); H01L 21/563 (2013.01); H01L 23/3157 (2013.01); H01L 23/367 (2013.01); H01L 23/49861 (2013.01); H01L 24/11 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 24/97 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16245 (2013.01); H01L 2924/182 (2013.01);
Abstract

In a described example, an apparatus includes: a first package substrate having a die mount surface; a semiconductor die flip chip mounted to the first package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the semiconductor die having solder bumps, wherein the solder bumps form solder joints to the package substrate; a second package substrate having a thermal pad positioned with the thermal pad over a backside surface of the semiconductor die, the thermal pad comprising a thermally conductive material; and a mold compound covering a portion of the first package substrate, a portion of the second package substrate, the semiconductor die, and the post connects, thermal pad having a surface exposed from the mold compound.


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