The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2024

Filed:

Feb. 04, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Wei Li, Chandler, AZ (US);

Edvin Cetegen, Chandler, AZ (US);

Nicholas S. Haehn, Scottsdale, AZ (US);

Mitul Modi, Phoenix, AZ (US);

Nicholas Neal, Gilbert, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/522 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3735 (2013.01); H01L 23/367 (2013.01); H01L 23/3736 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 23/5226 (2013.01); H01L 23/5384 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/81203 (2013.01);
Abstract

Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.


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