The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2024
Filed:
Jun. 11, 2021
Sandisk Technologies Llc, Addison, TX (US);
Fumitaka Amano, Yokkaichi, JP;
Yusuke Osawa, Yokkaichi, JP;
Kensuke Ishikawa, Yokkaichi, JP;
Mitsuteru Mushiga, Yokkaichi, JP;
Motoki Kawasaki, Yokkaichi, JP;
Shinsuke Yada, Yokkaichi, JP;
Masato Miyamoto, Yokkaichi, JP;
Syo Fukata, Yokkaichi, JP;
Takashi Kashimura, Yokkaichi, JP;
Shigehiro Fujino, Yokkaichi, JP;
SANDISK TECHNOLOGIES LLC, Addison, TX (US);
Abstract
A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity can be formed through the at least one via-level dielectric layer and one of the capping dielectric strips. A bit-line-contact via structure formed in the bit-line-contact via cavity includes a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer.