The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2024

Filed:

Feb. 28, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kelvin Tan Aik Boo, George Town, MY;

Chin Hui Chong, Braddell Hill, SG;

Seng Kim Ye, Fernvale Close, SG;

Hong Wan Ng, Singapore, SG;

Hem P. Takiar, Fremont, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 24/48 (2013.01); H01L 24/85 (2013.01); H01L 25/50 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/48229 (2013.01); H01L 2224/85045 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01);
Abstract

An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.


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