The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2024
Filed:
Jul. 08, 2021
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Zhi-Chang Lin, Hsinchu, TW;
Kuan-Ting Pan, Hsinchu, TW;
Shih-Cheng Chen, Hsinchu, TW;
Jung-Hung Chang, Hsinchu, TW;
Lo-Heng Chang, Hsinchu, TW;
Chien-Ning Yao, Hsinchu, TW;
Kuo-Cheng Chiang, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42392 (2013.01); H01L 29/0665 (2013.01); H01L 29/401 (2013.01); H01L 29/6653 (2013.01); H01L 29/78696 (2013.01);
Abstract
A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.